// link:https://gitee.com/xiwenx/uvm_learning/blob/master/UVM_demo/2.5.2/top_tb.sv
`timescale 1ns/1ps
// 1 包含UVM宏定义文件
`include "uvm_macros.svh"

// 1 导入UVM包的所有内容
import uvm_pkg::*;
// 2 导入uvm相关文件
`include "my_if.sv"
`include "my_transaction.sv"
`include "my_sequencer.sv"
`include "my_driver.sv"
`include "my_monitor.sv"
`include "my_agent.sv"
`include "my_model.sv"
`include "my_scoreboard.sv"
`include "my_env.sv"
`include "base_test.sv"
`include "my_case0.sv"
`include "my_case1.sv"

// 3 定义tb顶层
module top_tb;

reg clk;
reg rst_n;
reg[7:0] rxd;
reg rx_dv;
wire[7:0] txd;
wire tx_en;

my_if input_if(clk, rst_n);
my_if output_if(clk, rst_n);

// 4 实例化dut，并连接相关端口(clk、rst_n、input_if、output_if)
dut my_dut(.clk(clk),
           .rst_n(rst_n),
           .rxd(input_if.data),
           .rx_dv(input_if.valid),
           .txd(output_if.data),
           .tx_en(output_if.valid));

// 5 生成clk、rst_n信号
initial begin
   clk = 0;
   forever begin
      #100 clk = ~clk;
   end
end

initial begin
   rst_n = 1'b0;
   #1000;
   rst_n = 1'b1;
end

// 6 执行测试，这会调用执行命令时传入的UVM_TESTNAME参数指定的测试向量
initial begin
   run_test();
end

// 7 将端口传入UVM配置数据库中，供UVM组件使用
initial begin
   uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);
   uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if);
   uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if);
end

endmodule
